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  • Member for 9 years, 10 months
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16 votes

Difference between >> and >>> in verilog?

15 votes

RTL vs HDL? Whats the difference

6 votes

Why delays cannot be synthesized in Verilog?

6 votes
Accepted

Procedural blocks in verilog

5 votes

$random in Verilog doesn't seem to be working

4 votes

Blocking vs Non Blocking Assignments

3 votes

Blocking and Nonblocking statements in same procedural block

3 votes
Accepted

What is the set in D FF?

3 votes
Accepted

Verilog always block w/o posedge or negedge

3 votes

Help with $readmemb

3 votes

How to truncate an expression bit width in Verilog?

2 votes

Execute module one after another using flag status

2 votes

when do we use disable statement in verilog? is it possible to disable a block outside that block?

2 votes

always statement inside case in Verilog

2 votes

Understanding Verilog Netlist

2 votes
Accepted

Memory modelling and Memory module in Verilog synthesis

2 votes

How to wire output buses together

2 votes
Accepted

Read and write values in Multidimensional arrays in verilog

2 votes

what circuit the following verilog code produce

2 votes

Target <tr26> of concurrent assignment or output port connection should be a net type

2 votes

Understanding combinational feedback loops

2 votes
Accepted

Verilog assigning wire by iterating over array

1 vote

Test_bench in Verilog using Task

1 vote

Verilog: is connection without wires possible?

1 vote

Most efficient way to select between 10 large buses?

1 vote

Verilog inital value for flip flop

0 votes

value of variable in Veriog not defined