user avatar
user avatar
user avatar
JHBonarius
  • Member for 5 years, 6 months
  • Last seen more than a week ago
  • Netherlands
2 votes

VHDL bus keyword

2 votes

Delaying all incoming signals by 2 ms using VHDL

1 vote
Accepted

STD_LOGIC_VECTOR to INTEGER VHDL

1 vote
Accepted

Initialising FPGA internal RAM from file

1 vote

VHDL: I have a lot of inferring latches due to my case statement

1 vote
Accepted

this signal is connected to multiple drivers

1 vote
Accepted

My VHDL code is not processing an incoming signal correctly during a select set of time

0 votes

difference between sensitivity list and wait vhdl

0 votes
Accepted

Not understanding why "if" is not triggered in modelsim vhdl sim

0 votes

WARNING:Xst:1293 - FF/Latch <clkDiv/counter_1> has a constant value of 0 in block <DAC>. This FF/Latch will be trimmed during the optimization process

0 votes
Accepted

ERROR:Xst:827, Signal next_states1 cannot be synthesized, bad synchronous description

0 votes

Feedback in combinational digital circuits

-1 votes

How can i calculate the time that is elapsed between two sensors in vhdl?