Electrical Engineering
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Roman

Apparently, this user prefers to keep an air of mystery about them.

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  • Tomsk, Tomsk Oblast, Russia
  • Member for 2 years, 9 months
  • 26 profile views
  • Last seen Mar 12 '18 at 8:31

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Top posts (16) All Questions Answers | Votes Newest

2 Why I get 'u' even after initial the signal to '0'? Mar 27 '17
1 What logic function is implemented with these logic gates, how to complete truth table Apr 14 '17
1 VHDL Syntax Errors for Counter May 8 '17
1 How do I setup entity for a 1 to 2^n output demux with n select lines using VHDL? Mar 15 '17
1 VHDL simulation shows 'u' by read the input Mar 22 '17
1 Silly serial adder design with control unit Mar 24 '17
1 T-flip flop in Verilog Mar 26 '17
0 AXI master bus functional model in vhdl Feb 28 '17
0 What is VHDL analysis? Feb 28 '17
0 How to do simulation on modelsim 10.4 se? Feb 28 '17
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