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Roman's user avatar
Roman's user avatar
Roman
  • Member for 7 years, 1 month
  • Last seen more than 6 years ago
  • Tomsk, Tomsk Oblast, Russia
2 votes

Verilog RAM module with Register File & Testbench

2 votes

Why I get 'u' even after initial the signal to '0'?

1 vote
Accepted

What logic function is implemented with these logic gates, how to complete truth table

1 vote

VHDL Syntax Errors for Counter

1 vote

How do I setup entity for a 1 to 2^n output demux with n select lines using VHDL?

1 vote
Accepted

VHDL simulation shows 'u' by read the input

1 vote
Accepted

Silly serial adder design with control unit

1 vote

T-flip flop in Verilog

1 vote

U and the end of vector in iSIM

0 votes

Vhdl enable without clock question

0 votes

AXI master bus functional model in VHDL

0 votes

What is VHDL analysis?

0 votes

How to do simulation on modelsim 10.4 se?

0 votes
Accepted

Build Truth Table given Circuit

0 votes
Accepted

QUARTUS II: Error: Port "cg" does not exist in macro function "ADD0"

0 votes

Changing input values for every 2 clock cycles