User stanri

3 votes

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Apply PWM signal to PIN of a Microcontroller

answered Mar 11, 2013 at 9:40

3 votes

LED Breathing Effect

answered Apr 17, 2013 at 14:54

3 votes

Using SVN with Xilinx Vivado?

answered Jul 3, 2014 at 9:01

3 votes

Question regarding PCB design layout of Raspberry Pi

answered May 27, 2014 at 13:46

3 votes

Using Digital Clock Manager with Verilog to generate 25Mhz clock from 32Mhz internal clock

answered Jun 2, 2014 at 11:25

3 votes

Access NEON coprocessor from programmable logic in Zynq

answered Feb 8, 2016 at 7:39

3 votes

AXI stream slave

answered May 2, 2017 at 8:12

3 votes

VHDL: Converting from an INTEGER type to a STD_LOGIC_VECTOR

answered Jan 24, 2018 at 19:41

3 votes

How can I view, debug, or analyze data being input to my FPGA?

answered Feb 18, 2015 at 9:10

3 votes

Recursion in VHDL, performance? what is the difference with a conventional programming language?

answered Sep 21, 2015 at 11:03

2 votes

usb interface for fpga & Nios

answered Sep 14, 2015 at 8:12

2 votes

What is the meaning of performing logical operations on two numbers?

answered Feb 9, 2015 at 15:57

2 votes

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other uses of soft core in fpga applications?

answered Feb 10, 2015 at 5:01

2 votes

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Modelling Circuit from FSM using Verilog

answered Feb 8, 2016 at 9:21

2 votes

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Set a constant high signal to low

answered Jun 3, 2014 at 6:50

2 votes

Resistance, and learning for beginners

answered May 27, 2014 at 19:26

2 votes

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State switches in FSM

answered May 30, 2014 at 8:43

2 votes

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Best FPGA to work with

answered Apr 27, 2013 at 8:06

2 votes

Xilinx Vivado: [Common 17-53] User Exception: Unable to launch Synthesis run. No Verilog or VHDL sources found in project

answered Jul 2, 2014 at 17:15

2 votes

How to give a 2-D array as output of a function in Verilog?

answered Apr 11, 2013 at 15:41

2 votes

CPLD: my first project

answered Apr 28, 2014 at 6:28

2 votes

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VHDL top module problems

answered May 1, 2014 at 7:05

2 votes

VHDL: problem getting into state

answered May 3, 2014 at 14:21

2 votes

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Bad synchronous description error in VHDL

answered May 3, 2014 at 14:55

2 votes

How to Implement this special selector?

answered May 26, 2014 at 6:14

2 votes

What is the synthesizable VHDL method for loop or memory module?

answered Feb 24, 2013 at 9:37

2 votes

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12VDC power supply question

answered Feb 27, 2013 at 3:36

2 votes

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PCB footprint of Xilinx Kintex 7 FPGA

answered Feb 27, 2013 at 14:40

2 votes

Best way to build a 64-bit output multiplexer

answered Feb 19, 2013 at 5:03

2 votes

Math to predict current in circuit with different voltages in parallel

answered Feb 19, 2013 at 1:51

Stack Exchange Network

79 Answers

Apply PWM signal to PIN of a Microcontroller

LED Breathing Effect

Using SVN with Xilinx Vivado?

Question regarding PCB design layout of Raspberry Pi

Using Digital Clock Manager with Verilog to generate 25Mhz clock from 32Mhz internal clock

Access NEON coprocessor from programmable logic in Zynq

AXI stream slave

VHDL: Converting from an INTEGER type to a STD_LOGIC_VECTOR

How can I view, debug, or analyze data being input to my FPGA?

Recursion in VHDL, performance? what is the difference with a conventional programming language?

usb interface for fpga & Nios

What is the meaning of performing logical operations on two numbers?

other uses of soft core in fpga applications?

Modelling Circuit from FSM using Verilog

Set a constant high signal to low

Resistance, and learning for beginners

State switches in FSM

Best FPGA to work with

Xilinx Vivado: [Common 17-53] User Exception: Unable to launch Synthesis run. No Verilog or VHDL sources found in project

How to give a 2-D array as output of a function in Verilog?

CPLD: my first project

VHDL top module problems

VHDL: problem getting into state

Bad synchronous description error in VHDL

How to Implement this special selector?

What is the synthesizable VHDL method for loop or memory module?

12VDC power supply question

PCB footprint of Xilinx Kintex 7 FPGA

Best way to build a 64-bit output multiplexer

Math to predict current in circuit with different voltages in parallel