User stanri

18 votes

3 answers

3k views

Is it possible to have too much decoupling?

asked Jan 11, 2013 at 8:02

14 votes

4 answers

3k views

FPGA firmware design: How big is too big?

asked Dec 31, 2012 at 14:04

9 votes

3 answers

6k views

Schematic Critique: Phy interface with RJ45/Magnetics

asked Jan 10, 2013 at 14:26

9 votes

1 answer

2k views

What is the function of this choke-like transformer on the PCB side of this RJ45 jack+magnetics connector?

asked Jun 6, 2013 at 8:30

9 votes

2 answers

728 views

What would cause this kind of amplitude interference on my ADC recording?

asked Apr 6, 2018 at 8:32

7 votes

1 answer

874 views

What is lead-in termination?

asked Feb 9, 2013 at 5:17

6 votes

1 answer

6k views

3.3V IC <-> 2.5V FPGA IO Bank

asked Dec 6, 2012 at 10:36

5 votes

2 answers

3k views

MOSFET and clamp on I2C interface lines as level tranlastor

asked Jan 14, 2013 at 3:57

5 votes

2 answers

285 views

What is the electrical benefit of keeping a running disparity on a bus?

asked Jun 28, 2016 at 9:51

4 votes

2 answers

2k views

3.2 Gb/s high speed interface over 50m: copper, fiber, other ideas?

asked Nov 12, 2012 at 6:15

4 votes

2 answers

315 views

SDRAM chip selection

asked Nov 29, 2012 at 15:29

3 votes

1 answer

287 views

FPGA power usage estimate

asked Jan 17, 2013 at 5:04

3 votes

2 answers

7k views

Ethernet phy connection: grounding between chassis, connector and IO

asked Feb 12, 2013 at 3:13

3 votes

3 answers

819 views

32-way Mux Produces Horrible Timing Problems

asked Jun 26, 2014 at 17:51

2 votes

1 answer

4k views

Xilinx Vivado: [Common 17-53] User Exception: Unable to launch Synthesis run. No Verilog or VHDL sources found in project

asked Jul 2, 2014 at 17:15

2 votes

1 answer

2k views

Calculating the voltage generated by an 40KHZ Ultrasonic Tranceiver

asked Dec 9, 2013 at 15:11

2 votes

5 answers

5k views

Driving a 2V LED from a 1V8 FPGA IO pin (MOSFET vs open-drain)

asked Jan 31, 2013 at 5:22

2 votes

1 answer

827 views

How do I interpret the setup/hold time on this RMII interface?

asked May 16, 2019 at 9:29

2 votes

1 answer

4k views

Is it possible to drive a net from two processes when the assignments are conditionally mutually exclusive?

asked Mar 25, 2015 at 15:10

1 vote

1 answer

549 views

Addition in verilog: simulation doesn't match synthesis

asked Jul 17, 2015 at 18:18

1 vote

2 answers

4k views

What is a #delay inside a synchronous process used for?

asked Nov 19, 2015 at 8:21

1 vote

1 answer

1k views

how does bi-directional differential signalling work?

asked Feb 15, 2013 at 2:33

1 vote

1 answer

1k views

What is the minimum current I need to supply to a Spartan-6 pin in order to register a high signal?

asked Jan 2, 2013 at 6:56

1 vote

1 answer

2k views

RC pulldown on the MDI lines between the ethernet PHY and RJ45 Connector

asked Jan 4, 2013 at 10:37

0 votes

2 answers

857 views

daisy chain ethernet: performing arbitration on an FPGA

asked Jan 23, 2013 at 3:12

0 votes

1 answer

275 views

Is the simulated clock cycle latency through an entity accurate?

asked Jul 17, 2014 at 5:34

0 votes

1 answer

12k views

How is this ELCB connected to earth?

asked Apr 14, 2015 at 13:04

Stack Exchange Network

27 Questions

Is it possible to have too much decoupling?

FPGA firmware design: How big is too big?

Schematic Critique: Phy interface with RJ45/Magnetics

What is the function of this choke-like transformer on the PCB side of this RJ45 jack+magnetics connector?

What would cause this kind of amplitude interference on my ADC recording?

What is lead-in termination?

3.3V IC <-> 2.5V FPGA IO Bank

MOSFET and clamp on I2C interface lines as level tranlastor

What is the electrical benefit of keeping a running disparity on a bus?

3.2 Gb/s high speed interface over 50m: copper, fiber, other ideas?

SDRAM chip selection

FPGA power usage estimate

Ethernet phy connection: grounding between chassis, connector and IO

32-way Mux Produces Horrible Timing Problems

Xilinx Vivado: [Common 17-53] User Exception: Unable to launch Synthesis run. No Verilog or VHDL sources found in project

Calculating the voltage generated by an 40KHZ Ultrasonic Tranceiver

Driving a 2V LED from a 1V8 FPGA IO pin (MOSFET vs open-drain)

How do I interpret the setup/hold time on this RMII interface?

Is it possible to drive a net from two processes when the assignments are conditionally mutually exclusive?

Addition in verilog: simulation doesn't match synthesis

What is a #delay inside a synchronous process used for?

how does bi-directional differential signalling work?

What is the minimum current I need to supply to a Spartan-6 pin in order to register a high signal?

RC pulldown on the MDI lines between the ethernet PHY and RJ45 Connector

daisy chain ethernet: performing arbitration on an FPGA

Is the simulated clock cycle latency through an entity accurate?

How is this ELCB connected to earth?