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stanri
  • Member for 12 years, 1 month
  • Last seen more than a month ago
48 votes

Why aren't FPGAs ubiquitous?

27 votes
Accepted

How do you pronounce the following set of 'words'?

23 votes

n bit shift register (Serial Out) in VHDL

20 votes

How to divide 50MHz down to 2Hz in VHDL on Xilinx FPGA

16 votes

How do you document your hardware design decisions?

16 votes
Accepted

Sine signal generation using PWM

12 votes
Accepted

How to utilize HDMI port on FPGA (basic)

10 votes

Why would clipping a wire cause a bomb to explode?

9 votes

VHDL: Architecture naming and interpretation

9 votes
Accepted

Cutting and resoldering CPU chassis fan power cables

7 votes

i2c bus capacitance

7 votes

Procedural blocks in verilog

6 votes
Accepted

Can program FPGA but not PROM on my Spartan-3A dev board

6 votes
Accepted

State based vs State-less design (in verilog)

6 votes

I2C Issue at 400KHz

5 votes
Accepted

Please explain the following integer constant used in verilog

5 votes

When can FPGA's be used and Microcontrollers/DSPs not?

5 votes

When is the concurrent signal assignment executed?

4 votes

How does VHDL handle bitwise operations?

4 votes

ASIC vs ? -- Performance & Cost

4 votes
Accepted

Direction of Current Flow in the circuit?

4 votes
Accepted

Do I have to explicitly connect all pins of the ethernet chip in the FPGA when designing a new controller?

4 votes

What does "Sub-Miniature" really mean?

4 votes
Accepted

How do I calculate the correct resistor, capacitor for a low pass circuit?

4 votes
Accepted

Can I program a platform independent PLL in VHDL?

3 votes

Assigning ports of an n bit multiplexer

3 votes
Accepted

VHDL code not compiling

3 votes

Hardware solution to fade LED on/off with digital output

3 votes

Can I create a verilog file to both simulate and synthesize?

3 votes
Accepted

Carry Ripple Adder - VHDL