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Electrical Engineering
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lvd
  • Member for 11 years, 9 months
  • Last seen more than a month ago
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Top posts
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answer
4
Verilog: Break an always block
Nov 29, 2012
question
2
Auto-negotiation and link training in 10GBASE-R standards family
Oct 23, 2015
question
2
What is 1.27mm ribbon cable impedance for the "ground-signal-ground-signal-..." configuration?
Mar 20, 2020
answer
2
Is it possible to generate internal reset pulse in verilog with machxo3lf fpga?
Nov 6, 2018
answer
2
How to attenuate a cheap MP3-player speaker?
Jul 3, 2019
answer
2
Two-Channel PWM LED Driving at 12A Load Issue (Signals affect each other)
Jan 29, 2020
answer
2
Precision voltage clamping 0V to +5V with +/-12V input
Apr 7, 2020
answer
1
SD Card formatting in FAT 32 file system
Jul 4, 2019
answer
1
Ceramic capacitor 4kHz sound
Jan 30, 2020
answer
0
clocking on spartan6 FPGAs
Jan 28, 2015
Top network posts
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56
Zilog Z80 freezes while binary counting up to 65 536 (2^16)
39
What was the design rationale behind multi-port and multiple connections (and back-connections) designs of the early protocols like NFS or FTP?
25
Do instruction exercisers exist for 8086 and 68K (and other) CPUs?
24
Is there any advantage of a ceramic microprocessor over a plastic one?
23
What is the reason the 8051 was not used in 8-bit computers?