User Shine Sun

3 votes

2 answers

2k views

How do the D flip-flops in SAR logic work?

asked Sep 15, 2017 at 6:19

3 votes

1 answer

134 views

What will it happened when capacitance is almost the same as parasitic capacitance

asked Dec 20, 2017 at 12:46

2 votes

2 answers

1k views

What should i do with BJT when BJT has other two pins

asked Oct 12, 2017 at 12:12

2 votes

2 answers

148 views

Why does M4 turn off and Vout be equal to zero?

asked Feb 2, 2018 at 14:40

1 vote

1 answer

86 views

The reason why the output waveform of gate voltage boost is not almost the straight line?

asked Feb 4, 2018 at 12:13

1 vote

1 answer

300 views

The output buffer of sample and hold

asked Nov 2, 2017 at 1:07

1 vote

1 answer

936 views

Is it possible for (W/L) of 0.18nm PMOS to become 989100?

asked Aug 15, 2017 at 1:33

1 vote

1 answer

1k views

Is there a way to change only one of the outputs of a D flip-flop?

asked Sep 17, 2017 at 12:16

1 vote

0 answers

131 views

Is this a ring counter ? What is its definition?

asked Sep 20, 2017 at 12:19

0 votes

2 answers

551 views

The logic schematic which can change the duty cycle of input

asked Oct 11, 2017 at 11:44

0 votes

1 answer

67 views

Input of SAR logic

asked Sep 15, 2017 at 2:48

0 votes

1 answer

458 views

Little confuse about the truth table about D-flip flop

asked Sep 15, 2017 at 15:25

0 votes

2 answers

2k views

The problem about active low ,and how can i know it from the waveform

asked Sep 16, 2017 at 3:59

0 votes

0 answers

406 views

Design reset about top group of SAR logic

asked Sep 16, 2017 at 14:06

0 votes

0 answers

610 views

synchronous reset D flip-flop with three inputs

asked Jul 10, 2017 at 9:14

0 votes

3 answers

2k views

The method to get synchronous D-flip flop with three inputs,D,CLK and reset [duplicate]

asked Jul 10, 2017 at 23:06

0 votes

2 answers

967 views

Are the MUX with 3 inputs and AND with 2 inputs gate the same?

asked Jul 16, 2017 at 10:31

0 votes

0 answers

47 views

The difference between dual loop DC analysis and normal DC analysis

asked Jul 30, 2017 at 1:46

0 votes

2 answers

325 views

The current of M5 and M7 of two stage OTA

asked Aug 11, 2017 at 6:32

0 votes

2 answers

431 views

Why is the peak efficiency of most charge pump less than boost converter,but still can be published in IEEE [closed]

asked Feb 8, 2018 at 10:56

0 votes

1 answer

50 views

The reason why the output of ZCS-controlled boost converter is 1.2V,not 1V in this paper

asked Feb 11, 2018 at 5:11

0 votes

1 answer

81 views

LC oscillator V.S. LC oscillator deactivation

asked Feb 11, 2018 at 7:33

0 votes

1 answer

91 views

How to derive this formula from this schematic?

asked Feb 11, 2018 at 13:48

0 votes

1 answer

120 views

Input of boost converter or charge pump in the energy harvest [closed]

asked Feb 24, 2018 at 7:58

0 votes

0 answers

133 views

Circuit that can replace the ideal current source in the two stage amp

asked Nov 11, 2017 at 1:19

0 votes

1 answer

60 views

Change current of bandgap

asked Nov 11, 2017 at 11:27

0 votes

2 answers

300 views

Another solution for all MOS are in cutoff saturation region

asked Nov 14, 2017 at 4:44

0 votes

1 answer

377 views

The output of a SAR ADC

asked Nov 18, 2017 at 2:54

0 votes

1 answer

79 views

What kind of wave should i feed the input of sample and hold,which is in the sar adc

asked Nov 22, 2017 at 23:48

0 votes

2 answers

56 views

How do i decide the value of \$R\$,\$L\$ and \$K\$ in the bandgap when i want a specific \$V_{ref}\$

asked Nov 26, 2017 at 8:11

Stack Exchange Network

46 Questions

How do the D flip-flops in SAR logic work?

What will it happened when capacitance is almost the same as parasitic capacitance

What should i do with BJT when BJT has other two pins

Why does M4 turn off and Vout be equal to zero?

The reason why the output waveform of gate voltage boost is not almost the straight line?

The output buffer of sample and hold

Is it possible for (W/L) of 0.18nm PMOS to become 989100?

Is there a way to change only one of the outputs of a D flip-flop?

Is this a ring counter ? What is its definition?

The logic schematic which can change the duty cycle of input

Input of SAR logic

Little confuse about the truth table about D-flip flop

The problem about active low ,and how can i know it from the waveform

Design reset about top group of SAR logic

synchronous reset D flip-flop with three inputs

The method to get synchronous D-flip flop with three inputs,D,CLK and reset [duplicate]

Are the MUX with 3 inputs and AND with 2 inputs gate the same?

The difference between dual loop DC analysis and normal DC analysis

The current of M5 and M7 of two stage OTA

Why is the peak efficiency of most charge pump less than boost converter,but still can be published in IEEE [closed]

The reason why the output of ZCS-controlled boost converter is 1.2V,not 1V in this paper

LC oscillator V.S. LC oscillator deactivation

How to derive this formula from this schematic?

Input of boost converter or charge pump in the energy harvest [closed]

Circuit that can replace the ideal current source in the two stage amp

Change current of bandgap

Another solution for all MOS are in cutoff saturation region

The output of a SAR ADC

What kind of wave should i feed the input of sample and hold,which is in the sar adc

How do i decide the value of \$R\$,\$L\$ and \$K\$ in the bandgap when i want a specific \$V_{ref}\$