DonFusili's user avatar
DonFusili's user avatar
DonFusili's user avatar
DonFusili
  • Member for 6 years, 1 month
  • Last seen more than 2 years ago
  • Not Italy
6 votes

VHDL: difference between using "+" or writing our own adder

6 votes
Accepted

Is it possible to create a reusable full subtractor in SystemVerilog?

5 votes

"Tricking" ethernet cable it's disconnected

4 votes
Accepted

Is there anything macro-like, in VHDL?

3 votes

Edge vs Level Triggered Components

3 votes
Accepted

Clock Dividers with Clock Domain Crossing

3 votes

Can we connect both ASIC and an FPGA both to the same physical output Ethernet ports at the same time?

3 votes
Accepted

How to fix this VHDL error

3 votes

How to implement VHDL wait with timeout

3 votes
Accepted

why EDA industry has moved on from vhdl to verilog/system verilog?

2 votes
Accepted

How to have an in-system check in an FPGA based system that it has been reset?

2 votes

Beginner VHDL doubt

2 votes

VHDL integer to unsigned cast cost

2 votes

Warning!! Latch has unsafe behavior (vhdl)

2 votes

Why are accelerometers (and other MEMS devices) so rarely integrated into components?

2 votes

In CPFSK, suppose we transmit a continuous bit stream of 1, then for how long will the frequency go on increasing?

2 votes
Accepted

Rewrite logical combination expression

2 votes
Accepted

Clock Divider in VHDL Code

2 votes
Accepted

Strategy against Side Channel Attack

2 votes
Accepted

Is it inefficient or bad style to build std_logic_vector out of std_logic inputs?

2 votes

How can I make Lattice Symplify Pro infer RAM correctly from VHDL code?

1 vote
Accepted

Calculate CRC-16/Maxim in VHDL

1 vote

Why is there no latch in this circuit?

1 vote

Kirchhoff's laws circuit, How to calculate unknown resistor?

1 vote

Vending Machine - VHDL

1 vote
Accepted

VHDL 2 segments coding style sensitivity list issue - std_logic_vector at X value

1 vote

FPGA double buffer strategy

1 vote

First or last value checker component/funtion

1 vote

VHDL -- When is a process block too long?

1 vote
Accepted

VHDL ieee.numeric_std: Division by zero defined?