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andrsmllr

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Top posts (23) All Questions Answers | Votes Newest

10 What is a “half latch” in an FPGA? Jan 25 '18
8 How is a VHDL variable synthesized by synthesis tools Jun 21 '13
8 What is the use of 'event in vhdl? Jun 10 '15
7 What is the exact difference between SGMII and 1000Base-X? Dec 3 '14
4 Advantage of clock enable over clock division Mar 16 '16
3 Inferring BRAM with unused addresses efficiently Oct 24 '13
2 BlockRAM location constraints (Xilinx) Oct 23 '14
2 BlockRAM location constraints (Xilinx) Oct 27 '14
2 Identifier not declared in generic map, vhdl Nov 3 '15
2 Active serial configuration flash (EPCS & EPCQ) vs normal SPI flash Dec 2 '15
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