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andrsmllr
  • Member for 9 years, 9 months
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10 votes
Accepted

How is a VHDL variable synthesized by synthesis tools

10 votes
Accepted

What is the use of 'event in vhdl?

3 votes

Active serial configuration flash (EPCS & EPCQ) vs normal SPI flash

3 votes
Accepted

VHDL: Is it possible to have a "variable length" string in VHDL like in programming languages?

2 votes
Accepted

BlockRAM location constraints (Xilinx)

2 votes

Identifier not declared in generic map, vhdl

2 votes

LVDS-SPI bridge, asic or FPGA, and what FPGA

1 vote

Synthesising "constant" in VHDL

1 vote
Accepted

Constraint relative arrival time for a group of signals

1 vote

How to trigger at both edges in VHDL?

1 vote

VHDL - converting types and integer subtraction

0 votes

32-way Mux Produces Horrible Timing Problems

0 votes
Accepted

Error when creating a task in separate file in verilog

0 votes

Slow read from IST8308 via I2C using Python and smbus2