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avakar
  • Member for 14 years, 1 month
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Why does active-region process execute during program's #0 in Questa?
I agree that the for loop execution should not be interleaved execution in Active. My problem is that I'm seeing a different behavior in the simulator. I do have the standard, it's free through IEEE Get.
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How should deferred assertions behave in a combinatorial testbench?
While this resolves my confusion regarding the snippet in question, it creates a different confusion for me. Could you please have a look at electronics.stackexchange.com/questions/728081/… as well?
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How should deferred assertions behave in a combinatorial testbench?
I don't think there's a race though. The value of pass in $display(pass) should be captured at the point of queueing (in Active) and that value should be printed even if the action block executes in Reactive, possibly after pass was modified.
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How should deferred assertions behave in a combinatorial testbench?
Thank you! I completely missed the fact that not only must the entire Reactive region be drained before moving on, the entire reactive region set must be drained before moving on to Active. That also probably means that my attempts at completely getting rid of the concept of time when testing combinatorial modules are in vain.
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How to allow for custom vccio voltage?
@ChesterGillon That's actually perfect, thanks!
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How much does it cost to have a custom ASIC made?
@SteveSh I'm quite happy the answer was posted.
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