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BD_CE
  • Member for 5 years, 6 months
  • Last seen more than 5 years ago
4 votes
Accepted

Do Soft Termination Caps Really Increase Reliability?

4 votes
Accepted

I2S output in VHDL

3 votes

Connection of ESD return path the System GND

2 votes
Accepted

Advice for 25-50 Mbit SPI lines - PCB design

2 votes

Limited blind via pairs - Use for power or for signal?

2 votes
Accepted

How to reduce noise in SMPS (Switching mode power supply) circuit

2 votes

Capacitors in series, equivalent capacitance to reduce voltage rating

2 votes

EMC Testing, Radiated Emissions

1 vote

LED display flickering when connected to an ESP8266

1 vote

VHDL Output is Unitiliazed or Zero when simulated

1 vote

Using a microcontroller to produce a shock

1 vote
Accepted

PCB multiple ground planes

1 vote

How to cure SMPS output to get upset by a switching device

1 vote

Implementing a simple counter using VHDL

1 vote

ESD strike breaks the LAN8742A ethernet phy

1 vote

How to generate signal with glitches in VHDL?

1 vote

high power - overvoltage protection

0 votes

Issue with Booth multiplier VHDL code

0 votes

VHDL -- When is a process block too long?