User Martin Thompson

2 votes

Accepted

quartus signaltap not accurate?

answered Dec 1, 2014 at 13:14

2 votes

Interfacing FPGA and a storage device

answered Sep 19, 2014 at 8:41

2 votes

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FPGA : program that doesn't work everytime

answered Nov 18, 2015 at 16:39

2 votes

Why is the split termination method required for the CAN bus?

answered Apr 23, 2015 at 9:18

2 votes

VHDL Block RAM Inference

answered Apr 29, 2015 at 14:22

2 votes

How can I make a model of a single wire CAN bus cable?

answered Sep 20, 2018 at 15:32

2 votes

Using BRAM instead of SRAM in Virtex-5 FPGA

answered Feb 11, 2014 at 10:15

2 votes

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Will an SPI EEPROM chip have the same issues with non-atomic write operations as a dsPIC's internal EEPROM?

answered Mar 7, 2014 at 15:51

2 votes

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Retrieving samples from an FPGA using Ethernet

answered Mar 24, 2014 at 16:35

2 votes

Design practice crossing clock domains and async signals

answered Jan 15, 2014 at 21:12

2 votes

Why my FPGA programs does not work?

answered Nov 6, 2013 at 10:27

2 votes

Accepted

fgpa timing constraint on enable signal

answered Jan 10, 2014 at 13:05

2 votes

Avoiding crosstalk between makeshift wires

answered Apr 1, 2014 at 13:37

2 votes

VHDL - how to use inout as inout and as normal out?

answered Mar 27, 2014 at 14:06

2 votes

High speed memory interface between 2 FPGAs (Virtex 6)

answered Jul 15, 2014 at 15:17

2 votes

Why is Floating point non-synthesizable in verilog

answered Oct 18, 2013 at 8:45

2 votes

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FPGA Genetic algorithm

answered Sep 12, 2013 at 10:52

2 votes

How to implement FIR filter for Altera DE2?

answered Sep 17, 2013 at 8:01

2 votes

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Where did my state machine go?

answered Sep 27, 2013 at 14:15

2 votes

What is the meaning of speed grade marking on Xilinx FPGAs?

answered Nov 8, 2013 at 11:15

2 votes

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Custom FPGA PCB with external programming circuit

answered Nov 29, 2013 at 11:39

2 votes

Setting FPGA pins as virtual

answered Nov 29, 2013 at 14:24

2 votes

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Constraining the reset line

answered Dec 2, 2013 at 15:26

2 votes

PCIE reference clock

answered Dec 4, 2013 at 15:10

2 votes

Inferring Dual-Port Block RAM

answered Jul 19, 2013 at 8:12

2 votes

Generating pulse train of varying frequency on an FPGA

answered Aug 1, 2013 at 14:21

2 votes

FPGA Logic Gate Count

answered May 23, 2013 at 11:51

2 votes

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Improve my “From NAND to Tetris” ALU in VHDL

answered Apr 23, 2013 at 9:01

1 vote

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What to change when migrating designs from Altera DE2 to DE2-115?

answered Apr 29, 2013 at 10:45

1 vote

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Downsample vs custom latency register

answered Apr 30, 2013 at 14:16

Stack Exchange Network

258 Answers

quartus signaltap not accurate?

Interfacing FPGA and a storage device

FPGA : program that doesn't work everytime

Why is the split termination method required for the CAN bus?

VHDL Block RAM Inference

How can I make a model of a single wire CAN bus cable?

Using BRAM instead of SRAM in Virtex-5 FPGA

Will an SPI EEPROM chip have the same issues with non-atomic write operations as a dsPIC's internal EEPROM?

Retrieving samples from an FPGA using Ethernet

Design practice crossing clock domains and async signals

Why my FPGA programs does not work?

fgpa timing constraint on enable signal

Avoiding crosstalk between makeshift wires

VHDL - how to use inout as inout and as normal out?

High speed memory interface between 2 FPGAs (Virtex 6)

Why is Floating point non-synthesizable in verilog

FPGA Genetic algorithm

How to implement FIR filter for Altera DE2?

Where did my state machine go?

What is the meaning of speed grade marking on Xilinx FPGAs?

Custom FPGA PCB with external programming circuit

Setting FPGA pins as virtual

Constraining the reset line

PCIE reference clock

Inferring Dual-Port Block RAM

Generating pulse train of varying frequency on an FPGA

FPGA Logic Gate Count

Improve my “From NAND to Tetris” ALU in VHDL

What to change when migrating designs from Altera DE2 to DE2-115?

Downsample vs custom latency register