Electrical Engineering
Brian Carlton's user avatar
Brian Carlton's user avatar
Brian Carlton's user avatar
Brian Carlton
  • Member for 14 years, 1 month
  • Last seen more than a month ago
Profile Activity

16 Questions

Score Activity Newest Views
18 votes
3 answers
10k views

Good checklist for PCB design to be used by the EE (not by the PCB designer)

17 votes
4 answers
8k views

List of Xilinx file suffixes (for ISE)

17 votes
3 answers
12k views

Good schematic checklist

12 votes
4 answers
5k views

What standard PCB notes should I use?

12 votes
8 answers
6k views

After the PCB is designed, what do I need to check in the Gerber files?

7 votes
1 answer
1k views

What files/directories are needed to recreate a Xilinx PlanAhead project?

6 votes
5 answers
620 views

What is equivalent to a daily build (and smoke test) for schematic designs?

5 votes
2 answers
9k views

What are the various files types in Actel (Microsemi) Libero?

5 votes
1 answer
259 views

Why do spectrum analyzers generate X-Rays

4 votes
1 answer
765 views

What files/directories are needed to recreate a Actel/Microsemi Igloo2 project?

3 votes
2 answers
294 views

What are the files types used for Xilinx Vivado simulation

3 votes
1 answer
156 views

Do IBIS signal names need to be unique?

3 votes
3 answers
5k views

Suggested schematic check DRC settings for Tools>Verify in DxDesigner

2 votes
1 answer
5k views

What should be on a DVT (Design Verification Test) checklist?

2 votes
1 answer
1k views

Is there a free/low-cost bus monitor in VHDL/Verilog for ARM AXI/AXI4 and/or AXI4-Stream protocols?

0 votes
1 answer
107 views

List of files needed to rerun Aldec simulation?

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