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Electrical Engineering
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brunerm99
  • Member for 5 years, 9 months
  • Last seen more than 2 years ago
  • Colorado
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Electrical Engineer

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Confusion on what the RF input to a PLL does
Nov 10, 2021
question
2
Best practice for a single digital (SPI) line routed to multiple devices
Feb 9, 2022
question
1
Can phased-array (ULA) gain tapering effects be modelled using digital windows?
Jan 25, 2022
question
0
DDS output power
Nov 12, 2021
question
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PCB Layout - Option to power from LDOs or benchtop PSU
Feb 7, 2022