Electrical Engineering
shaiko's user avatar
shaiko's user avatar
shaiko's user avatar
shaiko
  • Member for 4 years, 11 months
  • Last seen this week
Profile Activity
Stats
459
reputation
39k
reached
0
answers
20
questions
Communities
View all
Badges
View all badges
1
gold badge
6
silver badges
15
bronze badges
Top tags
View all tags
0
Score
13
Posts
65
Posts %
0
Score
10
Posts
50
Posts %
0
Score
2
Posts
10
Posts %
0
Score
2
Posts
10
Posts %
0
Score
2
Posts
10
Posts %
0
Score
2
Posts
10
Posts %
Top posts
View all questions and answers
All Questions Answers
Score Newest
question
5
Nonblocking ++ equivalent in SystemVerilog
Feb 14, 2021
question
4
PID - Integrator Anti Windup limit values
Dec 31, 2018
question
4
Inherent Pseudo-Randomness in modern FPGA design tools
May 1, 2019
question
3
Apostrophe in Verilog array assignment
Sep 6, 2020
question
3
Gray code usage in modulation constellations
Oct 20, 2020
question
3
Multiple driver error for SystemVerilog initial value
Mar 15, 2021
question
2
Verilog for loop - genvar vs int
Sep 9, 2020
question
2
QPSK Modulation towards DAC
Aug 11
question
1
Systemverilog size attributes
May 30, 2020
question
1
BALUN vs other methods
Jun 15, 2020
Top network posts
View all network posts
23
Why is the graphite moderator in a nuclear reactor radioactive?

Your privacy

By clicking “Accept all cookies”, you agree Stack Exchange can store cookies on your device and disclose information in accordance with our Cookie Policy.