User Arseniy

42 votes

2 answers

9k views

Why do banana plugs need these holes?

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asked Sep 7, 2020 at 10:21

23 votes

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2 votes

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170 views

Is it possible to make hierarchy of constants in System Verilog?

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2 votes

3 answers

397 views

Is it a good practice to define TRUE/FALSE constants in SystemVerilog?

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2 votes

1 answer

317 views

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2 votes

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41 views

How to measure the I-V characteristic for IBIS-model?

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asked Dec 2, 2021 at 13:03

2 votes

0 answers

46 views

Is there a single word term for doubled amplitude of square wave?

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asked Feb 9 at 10:56

1 vote

1 answer

155 views

How to parameterize a clock divider?

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asked Mar 25, 2021 at 14:11

1 vote

0 answers

34 views

Is there a standard that describes the term "coplanar waveguide"?

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asked Feb 3 at 6:44

1 vote

2 answers

113 views

What are the reasons to use SWR instead of the reflection coefficient?

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asked Dec 21, 2021 at 8:37

1 vote

1 answer

140 views

How long can a DDR memory row be activated?

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asked Jun 15, 2021 at 14:28

1 vote

4 answers

239 views

How can I match a transmission line impedance on the source side?

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asked Aug 12, 2021 at 15:54

1 vote

3 answers

390 views

What is the maximum frequency of CMOS level triangle wave?

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asked Mar 28, 2020 at 10:33

0 votes

2 answers

440 views

Is it necessary to declare reg before assignment in Verilog?

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asked Apr 24, 2020 at 6:30

0 votes

1 answer

2k views

How to create a nested for-loop in Verilog?

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0 votes

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What is the best method to transmit a DVI-D video signal from a FPGA?

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asked Nov 3, 2020 at 15:51

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76 views

Where can I find IC packages list wich used in BSDL files?

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asked Aug 20, 2019 at 6:46

0 votes

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221 views

What is the maximum frequency to use diodes for distortion?

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asked Feb 23, 2020 at 18:12

0 votes

1 answer

89 views

Why am I not receiving a 60 MHz signal from CLKOUT in sync.FIFO mode on the FT2232H?

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asked Mar 23, 2020 at 14:38

0 votes

0 answers

44 views

Does HyperLynx have an impedance calculator for coplanar waveguide?

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asked Oct 30, 2021 at 19:20

0 votes

4 answers

110 views

How to name the frequency of digital signal?

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asked Feb 2 at 8:22

0 votes

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23 views

What is the value that captured into BYPASS register?

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asked Apr 8 at 7:49

0 votes

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67 views

Why do the JTAG parallel registers update on the falling edge?

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asked Apr 15 at 16:21

0 votes

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56 views

+50

Is it possible to display a custom error message in Synplify syntezis with SystemVerilog code?

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asked Jun 22 at 11:54

-1 votes

3 answers

115 views

Why use multiple regulators?

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asked Dec 10, 2020 at 7:38

-2 votes

1 answer

88 views

Why is BSDL syntax so wordy?

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asked Apr 3 at 10:03

-7 votes

1 answer

390 views

Will RTOS's be displace by FPGA's? [closed]

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asked Jun 26, 2020 at 8:52

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27 Questions

Why do banana plugs need these holes?

Why does RAM (any type) access time decrease so slowly?

Is it possible to make hierarchy of constants in System Verilog?

Is it a good practice to define TRUE/FALSE constants in SystemVerilog?

Must an SV inout port be only in the top module?

How to measure the I-V characteristic for IBIS-model?

Is there a single word term for doubled amplitude of square wave?

How to parameterize a clock divider?

Is there a standard that describes the term "coplanar waveguide"?

What are the reasons to use SWR instead of the reflection coefficient?

How long can a DDR memory row be activated?

How can I match a transmission line impedance on the source side?

What is the maximum frequency of CMOS level triangle wave?

Is it necessary to declare reg before assignment in Verilog?

How to create a nested for-loop in Verilog?

What is the best method to transmit a DVI-D video signal from a FPGA?

Where can I find IC packages list wich used in BSDL files?

What is the maximum frequency to use diodes for distortion?

Why am I not receiving a 60 MHz signal from CLKOUT in sync.FIFO mode on the FT2232H?

Does HyperLynx have an impedance calculator for coplanar waveguide?

How to name the frequency of digital signal?

What is the value that captured into BYPASS register?

Why do the JTAG parallel registers update on the falling edge?

Is it possible to display a custom error message in Synplify syntezis with SystemVerilog code?

Why use multiple regulators?

Why is BSDL syntax so wordy?

Will RTOS's be displace by FPGA's? [closed]