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Arseniy
  • Member for 3 years, 4 months
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  • Moscow, Россия
42 votes
2 answers
9k views

Why do banana plugs need these holes?

23 votes
3 answers
6k views

Why does RAM (any type) access time decrease so slowly?

2 votes
2 answers
169 views

Is it possible to make hierarchy of constants in System Verilog?

2 votes
3 answers
391 views

Is it a good practice to define TRUE/FALSE constants in SystemVerilog?

2 votes
1 answer
313 views

Must an SV inout port be only in the top module?

2 votes
1 answer
41 views

How to measure the I-V characteristic for IBIS-model?

2 votes
0 answers
46 views

Is there a single word term for doubled amplitude of square wave?

1 vote
1 answer
155 views

How to parameterize a clock divider?

1 vote
0 answers
34 views

Is there a standard that describes the term "coplanar waveguide"?

1 vote
2 answers
113 views

What are the reasons to use SWR instead of the reflection coefficient?

1 vote
1 answer
139 views

How long can a DDR memory row be activated?

1 vote
4 answers
239 views

How can I match a transmission line impedance on the source side?

1 vote
3 answers
390 views

What is the maximum frequency of CMOS level triangle wave?

0 votes
2 answers
438 views

Is it necessary to declare reg before assignment in Verilog?

0 votes
1 answer
2k views

How to create a nested for-loop in Verilog?

0 votes
1 answer
539 views

What is the best method to transmit a DVI-D video signal from a FPGA?

0 votes
0 answers
76 views

Where can I find IC packages list wich used in BSDL files?

0 votes
2 answers
221 views

What is the maximum frequency to use diodes for distortion?

0 votes
1 answer
89 views

Why am I not receiving a 60 MHz signal from CLKOUT in sync.FIFO mode on the FT2232H?

0 votes
0 answers
44 views

Does HyperLynx have an impedance calculator for coplanar waveguide?

0 votes
4 answers
110 views

How to name the frequency of digital signal?

0 votes
1 answer
23 views

What is the value that captured into BYPASS register?

0 votes
2 answers
66 views

Why do the JTAG parallel registers update on the falling edge?

0 votes
0 answers
46 views
+50

Is it possible to display a custom error message in Synplify syntezis with SystemVerilog code?

-1 votes
3 answers
115 views

Why use multiple regulators?

-2 votes
1 answer
88 views

Why is BSDL syntax so wordy?

-7 votes
1 answer
389 views

Will RTOS's be displace by FPGA's? [closed]