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Jules
  • Member for 11 years
  • Last seen more than a month ago
17 votes
2 answers
2k views

Parallel RAM without large number of pins?

12 votes
3 answers
9k views

Is there a way of conditionally triggering a compile-time error in verilog?

6 votes
2 answers
317 views

Making my own PCB connectors, but having trouble with high frequency signals

6 votes
3 answers
2k views

Heatsink earthing?

3 votes
1 answer
2k views

ModelSim Altera: simulating the "lpm_add_sub" module?

3 votes
1 answer
221 views

Design of a differential digital signal buffer, 250MHz, 1V output swing

3 votes
4 answers
404 views

Simulating Altera FPGAs with an old version of ModelSim?

2 votes
2 answers
2k views

Icarus verilog syntax error in a generate block

2 votes
1 answer
1k views

How can I program GALs on a shoestring budget?

2 votes
1 answer
223 views

How to replace TTL PROMs in a design operating at 20MHz

2 votes
1 answer
140 views

Can a Z84C00 CPU directly drive 74HCxxx series logic?

1 vote
1 answer
724 views

How to simulate a FIFO in Logisim

1 vote
1 answer
117 views

register enable line usage in `case` block (verilog synthesis for altera cpld)

0 votes
1 answer
208 views

Unexpected indeterminate outputs from verilog conditional operator