Electrical Engineering
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Martel
  • Member for 3 years, 1 month
  • Last seen this week
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All Questions Answers
Score Newest
question
13
In FPGAs, is it safe to execute non-blocking assignments like `b <= a; a <= 0;` in the same clock cycle?
Nov 12, 2021
question
10
Does the SPI protocol specify how many clock pulses a master device should send to the slave?
Nov 9, 2021
question
5
Charge pump has an unexpected voltage drop with a 1K load
Apr 30, 2021
question
5
Don't understand MOSFET as amplifier
Aug 20, 2019
question
3
What is "voltage output swing from rail" in a TI op. amp. datasheet?
May 12, 2021
question
3
Ternary operator doesn't work in Icarus Verilog
Dec 30, 2021
question
3
Is it necessary to take into account the actual state of a combinational circuit's signals to calculate its maximum delay?
Apr 2
question
2
Correct way of estimating delays in FPGAs
Apr 28
question
2
Is it acceptable to gate an SPI clock (sck) to disable it when ss is high? (in an FPGA)
Jun 21
question
2
How to understand this combinational cyclic circuit made of interconnected SR latches?
Jan 30
Top network posts
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16
Is it ok to upvote everyone that answers my question, or leaves a comment, just to appreciate the time they spent writing?
6
Understanding the past growth of an ETF
6
How to find the trading costs in an ETF prospectus
6
Can fundamental analysis be applied to market indexes as if they were single stocks/bonds?

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