Electrical Engineering
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Sittin Hawk

Apparently, this user prefers to keep an air of mystery about them.

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  • Member for 1 year, 3 months
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5 negative miller capacitance Jan 18 '20
4 Attach output to a state in Finite State Machine in VHDL Nov 30 '19
3 Impedance/Termination of Marvell PHY Oct 5 '20
2 Application of set_clock_latency Apr 10 '20
2 Clock generation on FPGA pin Apr 21 '20
1 SFP+ 10GbE Module Interface Jun 30 '20
1 DG flip-flop behavior? Dec 12 '20
1 BJT low frequency analysis Jan 11 '20
1 Op-Amp Unity Gain Frequency Feb 1 '20
1 Gain bandwidth product for amplifier Feb 13 '20
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