Electrical Engineering
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Sittin Hawk

Apparently, this user prefers to keep an air of mystery about them.

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5 negative miller capacitance Jan 18
4 Attach output to a state in Finite State Machine in VHDL Nov 30 '19
3 Impedance/Termination of Marvell PHY Oct 5
2 Application of set_clock_latency Apr 10
2 Clock generation on FPGA pin Apr 21
1 SFP+ 10GbE Module Interface Jun 30
1 I want to implement an Adder for 8-bit signed numbers coded with 1’s Complement representation Nov 30 '19
1 what is the most difficult part of creating a DDR2 or DDR3 memory controller inside an FPGA? Oct 5
1 BJT low frequency analysis Jan 11
1 Op-Amp Unity Gain Frequency Feb 1
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