Electrical Engineering
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tim
  • Member for 3 years, 7 months
  • Last seen more than a month ago
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All Questions Answers
Score Newest
answer
5
How can I avoid a clock glitch?
Dec 19, 2020
answer
3
Debounce circuit design in Verilog
Jun 17, 2020
answer
3
Can someone help me understand this code for the ADXL345 accelerometer?
Apr 7, 2022
answer
3
Why does “non blocking” assignment in Verilog seem like a misnomer?
Aug 28, 2021
answer
3
High side mosfet 12V switch from isolated 3V3 GPIO
May 27, 2021
answer
3
Does VHDL allow port mapping of a single bit output to multiple bits driven to same value, in one line?
Jul 21, 2020
answer
3
How can I debounce a switch on both positive and negative-going edges?
Mar 12, 2021
answer
3
Interface to numpad in VHDL. Numlock button support
Sep 6, 2020
answer
3
OR gates used as NOT
Mar 11, 2021
answer
3
How can I make an XOR gate with basic components?
Sep 13, 2020
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How do I make another action repeat inside a loop?

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