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tim
  • Member for 2 years, 2 months
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6 votes

How can I avoid a clock glitch?

3 votes

How to write scalable VHDL code

3 votes

OR gates used as NOT

3 votes
Accepted

Interface to numpad in VHDL. Numlock button support

3 votes

How can I make an XOR gate with basic components?

3 votes
Accepted

VHDL Clock Divider Problem

3 votes

High side mosfet 12V switch from isolated 3V3 GPIO

3 votes

Why does “non blocking” assignment in Verilog seem like a misnomer?

3 votes

Can someone help me understand this code for the ADXL345 accelerometer?

2 votes

I2C pin SCL line go to low any random time

2 votes
Accepted

Verilog counting problem - posedge detector with if statement not working as expected

2 votes
Accepted

Connecting potentiometer to an FPGA simply

2 votes

Failed to use a low pass filter in order to convert PWM input to digital output

2 votes

Debounce circuit design in Verilog

2 votes
Accepted

Does VHDL allow port mapping of a single bit output to multiple bits driven to same value, in one line?

2 votes

I think I found an error in an electronics book. Are my equations correct here?

2 votes

How can I debounce a switch on both positive and negative-going edges?

1 vote

Opposite of reflection coefficient

1 vote

VHDL Counter not Working

1 vote

32 bit to 7 segment display (FPGA)

1 vote
Accepted

How to monitor FPGA signals on the simulator

1 vote

'1011' Overlapping (Mealy) Sequence Detector in Verilog

1 vote

Unable to use IR receiver and motor shield together

1 vote

Current sense resistor for high voltage

1 vote

High or low side switching where the switch (button) is meters away from the circuit

1 vote

How to time inputs into a circuit

1 vote

Initialise ADC with VHDL

1 vote

Elegant way to check a STD_LOGIC_VECTOR to be all zero

1 vote

VHDL: Converting from an INTEGER type to a STD_LOGIC_VECTOR

0 votes

What's the best way to debounce a slider switch?