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Electrical Engineering
Abhishek Chunduri's user avatar
Abhishek Chunduri's user avatar
Abhishek Chunduri's user avatar
Abhishek Chunduri
  • Member for 4 years, 7 months
  • Last seen more than 2 years ago
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Currently a 2nd Year Avionics Student at IIST, with key interest in Programming, Electronics hardware design ,Robotics & PCB Designs.

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View all questions and answers
question
5
'1011' Overlapping (Mealy) Sequence Detector in Verilog
Jun 16, 2020
question
5
'1011' Overlapping (Moore) Sequence Detector in Verilog
Jun 16, 2020
question
3
Error: HDL Compiler : 1660 : Procedural assignment to a non-register big_mant is not permitted, left-hand side should be reg/integer/time/genvar
May 7, 2020
question
2
Synthesizing error while designing 4-bit ALU in Verilog
May 21, 2020
question
2
Debounce circuit design in Verilog
Jun 16, 2020
question
1
Error: HDL-Complier-661 Non-net port cannot be mode of input
May 6, 2020
question
1
Error while implemeting D_FF from JK_FF in Verilog
May 31, 2020
answer
1
Debounce circuit design in Verilog
Jun 18, 2020
question
0
Phase of grid current is not varying in the simple RL circuit
Mar 15, 2022
answer
0
Error: HDL-Complier-661 Non-net port cannot be mode of input
May 7, 2020