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lousycoder
  • Member for 3 years, 10 months
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1 vote
2 answers
68 views

Final non-blocking assignment to a register in case of parallel if-else statement in Verilog

4 votes
2 answers
161 views

Interaction between multiple blocking assignment and non-blocking assignment running in separate procedural blocks in Verilog

0 votes
1 answer
62 views

Guidelines for reducing levels of logic cells in FPGAs while using HDL operators in behavioral modelling

3 votes
2 answers
123 views

Why non-blocking assignments in Verilog sometimes do not provide a clock cycle delay?

1 vote
1 answer
186 views

How do I create custom signal in waveform config file for a big Boolean expression made of many signals/expressions in an "if else" block in Vivado?

-1 votes
2 answers
103 views

Verilog keyword for "please refer to previous assignment?" in case of non-blocking assignment?

0 votes
1 answer
350 views

SystemVerilog array of parameters/constants

1 vote
1 answer
82 views

Navigating race condition in Verilog using blocking assignment

0 votes
1 answer
51 views

How much is the video timing error allowance in DisplayPort?

2 votes
5 answers
702 views

How do I get more clarity on the meaning of "integration" in VLSI?

0 votes
2 answers
539 views

How do I visualize Verilog/HDL simulation?

1 vote
2 answers
513 views

How do I interpret DisplayPort blanking interval timing diagrams?

1 vote
2 answers
102 views

Do wire/net type constructs in Verilog map to programmable interconnects/ switching matrix of FPGA?

0 votes
1 answer
611 views

classic RISC pipeline: Why does memory access stage comes before register file write back?

0 votes
1 answer
152 views

More clarity on Verilog Non-Blocking assignments

0 votes
1 answer
459 views

What is the maximum number of inputs to a logic gate that is being used in computing hardware these days?

0 votes
1 answer
198 views

What is exactly a transaction initiator and executor in UVM port and export?

0 votes
2 answers
253 views

Where do the procedural block etc. lie in Verilog timing region?

-3 votes
1 answer
145 views

Can color blindness be a disqualifying factor for a person applying for chip layout engineer positions? [closed]

1 vote
1 answer
311 views

SSD lifespan is often expressed in terms of TBW (Terabytes Written), does that include read cycles?

10 votes
3 answers
2k views

How were custom chips designed in the days prior to the arrival of FPGAs as hardware emulation devices? [closed]

9 votes
4 answers
4k views

How does the current processor technology with low clock rates (<10 GHz) deals with mmWave (>10 GHz) technology used in 5G?

-2 votes
1 answer
260 views

why EDA industry has moved on from vhdl to verilog/system verilog? [closed]