Skip to main content
lousycoder's user avatar
lousycoder's user avatar
lousycoder's user avatar
lousycoder
  • Member for 3 years, 9 months
  • Last seen more than a week ago
  • India
9 votes
4 answers
4k views

How does the current processor technology with low clock rates (<10 GHz) deals with mmWave (>10 GHz) technology used in 5G?

10 votes
3 answers
2k views

How were custom chips designed in the days prior to the arrival of FPGAs as hardware emulation devices? [closed]

2 votes
5 answers
701 views

How do I get more clarity on the meaning of "integration" in VLSI?

0 votes
1 answer
598 views

classic RISC pipeline: Why does memory access stage comes before register file write back?

0 votes
2 answers
526 views

How do I visualize Verilog/HDL simulation?

1 vote
2 answers
496 views

How do I interpret DisplayPort blanking interval timing diagrams?

0 votes
1 answer
444 views

What is the maximum number of inputs to a logic gate that is being used in computing hardware these days?

1 vote
1 answer
306 views

SSD lifespan is often expressed in terms of TBW (Terabytes Written), does that include read cycles?

0 votes
1 answer
290 views

SystemVerilog array of parameters/constants

-2 votes
1 answer
253 views

why EDA industry has moved on from vhdl to verilog/system verilog? [closed]

0 votes
2 answers
245 views

Where do the procedural block etc. lie in Verilog timing region?

0 votes
1 answer
195 views

What is exactly a transaction initiator and executor in UVM port and export?

1 vote
1 answer
174 views

How do I create custom signal in waveform config file for a big Boolean expression made of many signals/expressions in an "if else" block in Vivado?

4 votes
2 answers
156 views

Interaction between multiple blocking assignment and non-blocking assignment running in separate procedural blocks in Verilog

-3 votes
1 answer
144 views

Can color blindness be a disqualifying factor for a person applying for chip layout engineer positions? [closed]

0 votes
1 answer
124 views

More clarity on Verilog Non-Blocking assignments

3 votes
2 answers
120 views

Why non-blocking assignments in Verilog sometimes do not provide a clock cycle delay?

-1 votes
2 answers
103 views

Verilog keyword for "please refer to previous assignment?" in case of non-blocking assignment?

1 vote
2 answers
101 views

Do wire/net type constructs in Verilog map to programmable interconnects/ switching matrix of FPGA?

1 vote
1 answer
80 views

Navigating race condition in Verilog using blocking assignment

1 vote
2 answers
68 views

Final non-blocking assignment to a register in case of parallel if-else statement in Verilog

0 votes
1 answer
60 views

Guidelines for reducing levels of logic cells in FPGAs while using HDL operators in behavioral modelling

0 votes
1 answer
50 views

How much is the video timing error allowance in DisplayPort?