Electrical Engineering
IanJ's user avatar
IanJ's user avatar
IanJ's user avatar
IanJ
  • Member for 2 years, 6 months
  • Last seen more than 1 year ago
Profile Activity
Stats
319
reputation
6k
reached
12
answers
0
questions
Communities
View all
Badges
This user doesn’t have any gold badges yet.
1
silver badge
4
bronze badges
Top tags
View all tags
11
Score
2
Posts
17
Posts %
10
Score
3
Posts
25
Posts %
9
Score
1
Posts
8
Posts %
7
Score
6
Posts
50
Posts %
3
Score
1
Posts
8
Posts %
2
Score
4
Posts
33
Posts %
Top posts
View all questions and answers
All Questions Answers
Score Newest
answer
9
Verilog odd behavior with multiple edge detect
Mar 15, 2021
answer
3
SPI clock signal (SCLK) usage in FPGA SPI slave
Mar 18, 2021
answer
2
Problem mapping VHDL onto development board
Dec 18, 2020
answer
1
How can the FPGA design induce a system wide reset?
Dec 19, 2020
answer
1
Verilog Non-Blocking And IF-Statement
Feb 11, 2021
answer
1
Stepper Driver pulses control (with Arduino)
Feb 20, 2021
answer
1
How to hash map known values to smaller data width?
May 29, 2021
answer
0
Initialise ADC with VHDL
Nov 26, 2020
answer
0
5V to 12V DC-DC converter to power an 11 watt bulb
Jan 16, 2021
answer
0
Is there a proper way in VHDL/Verilog to access block RAM given a multi-hot vector?
Jan 16, 2021
Top network posts
View all network posts
5
How can I get this broken oil drain cover off?

Your privacy

By clicking “Accept all cookies”, you agree Stack Exchange can store cookies on your device and disclose information in accordance with our Cookie Policy.