User IanJ - Electrical Engineering Stack Exchange

IanJ

Member for 3 years
Last seen more than 2 years ago

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12 Answers

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9 votes

Accepted

Verilog odd behavior with multiple edge detect

answered Mar 15, 2021 at 22:00

3 votes

SPI clock signal (SCLK) usage in FPGA SPI slave

answered Mar 18, 2021 at 23:10

2 votes

Problem mapping VHDL onto development board

answered Dec 18, 2020 at 22:20

1 vote

How can the FPGA design induce a system wide reset?

answered Dec 19, 2020 at 0:16

1 vote

Verilog Non-Blocking And IF-Statement

answered Feb 11, 2021 at 2:05

1 vote

Stepper Driver pulses control (with Arduino)

answered Feb 20, 2021 at 1:19

1 vote

How to hash map known values to smaller data width?

answered May 29, 2021 at 14:54

0 votes

Moving AI IP into new FPGA. Is the trigger for reading ROM an address change?

answered Apr 11, 2021 at 15:44

0 votes

Initialise ADC with VHDL

answered Nov 26, 2020 at 18:58

0 votes

Accepted

VHDL code for ALU and ROM connection

answered Feb 15, 2021 at 15:54

0 votes

5V to 12V DC-DC converter to power an 11 watt bulb

answered Jan 16, 2021 at 16:10

0 votes

Is there a proper way in VHDL/Verilog to access block RAM given a multi-hot vector?

answered Jan 16, 2021 at 16:33