Electrical Engineering
JCLL's user avatar
JCLL's user avatar
JCLL's user avatar
JCLL
  • Member for 12 years, 10 months
  • Last seen this week
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10
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23
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Top posts
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All Questions Answers
Score Newest
question
8
What is a fractional-order circuit?
Oct 3, 2013
question
3
How many transistors/logic gates are used in the signal path between a TV studio and the restitution of the image on my HD-TV?
Jan 22, 2011
question
3
Is it still possible to find Braun Lectron System around, or equivalent? [closed]
Jan 1, 2013
question
3
How can I avoid "Minimum Pulse Width" slack violations in Quartus FPGA synthesis?
Jan 28, 2013
answer
3
Can oscillations occur in VHDL with concurrent statements?
Oct 29, 2014
question
2
Why two Xilinx scripts with different bitgen options yield correct and incorrect behaviors?
Oct 10, 2014
question
1
Different Altera DE2 boards do not behave the same way
Jan 18, 2013
question
1
How to best synthesize a systolic circuit on FPGA?
Nov 16, 2014
question
1
Addition of 2 unsigned values in VHDL IEEE numeric_std : why this choice?
Nov 12, 2018
answer
1
Different Altera DE2 boards do not behave the same way
Jan 20, 2013
Top network posts
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102
Are GCC and Clang parsers really handwritten?
49
How to change all the keys of a hash by a new set of given keys
47
How to install a downloaded Ruby gem file?
31
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19
Creating a VHDL backend for LLVM?

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