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Electrical Engineering
Martel's user avatar
Martel's user avatar
Martel's user avatar
Martel
  • Member for 5 years, 6 months
  • Last seen this week
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67
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Top posts
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question
13
In FPGAs, is it safe to execute non-blocking assignments like `b <= a; a <= 0;` in the same clock cycle?
Nov 12, 2021
question
10
Does the SPI protocol specify how many clock pulses a master device should send to the slave?
Nov 9, 2021
question
6
Vivado constraints wizard suggests a lot of nonsense generated clocks
Oct 11, 2022
question
5
Don't understand MOSFET as amplifier
Aug 20, 2019
question
5
Help calculating and simulating buck converter
Nov 3
question
5
Charge pump has an unexpected voltage drop with a 1K load
Apr 30, 2021
question
4
Don't understand the current direction in a flyback diode circuit
Jan 9, 2021
question
3
Is it necessary to take into account the actual state of a combinational circuit's signals to calculate its maximum delay?
Apr 2, 2022
question
3
Ternary operator doesn't work in Icarus Verilog
Dec 30, 2021
question
3
What is "voltage output swing from rail" in a TI op-amp datasheet?
May 12, 2021
Top network posts
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39
Is it ok copying code from one application to another, both belonging to the same repository, to keep them independent?
23
Compiler doesn't fail when pushing back a std::unique_ptr into a std::vector
16
Is it ok to upvote everyone that answers my question, or leaves a comment, just to appreciate the time they spent writing?
15
Ignore certain files when using clang-tidy
10
Understanding linker script NOLOAD sections in embedded software