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kevin998x
  • Member for 10 years, 3 months
  • Last seen more than 2 years ago
4 votes
1 answer
458 views

telephone hold-on music

3 votes
1 answer
174 views

Frequency Divider Analog Circuit issue

3 votes
1 answer
545 views

Constant-gm bias circuit

2 votes
1 answer
570 views

gilbert cell mixer implementation and balun

2 votes
3 answers
2k views

Why 1.5x ratio limitation for synchronizing slow signals into fast clock domain?

2 votes
2 answers
631 views

USB Softcore for FPGA : Extra resistor on FPGA transmitter pin

2 votes
3 answers
467 views

Measuring transconductance of any circuit

1 vote
0 answers
161 views

dc sweep convergence issue for cmos inverter

1 vote
3 answers
191 views

zero AC gain of CMOS inverter

1 vote
1 answer
313 views

Periodic Steady State analysis for class C amplifier

1 vote
2 answers
611 views

Smith chart of λ/4 Transmission Line

1 vote
0 answers
314 views

Schematic diagram of a double-balanced Gilbert cell mixer

1 vote
1 answer
463 views

Glitches in clock gating cell

1 vote
0 answers
3k views

pseudo transient analysis issue

1 vote
1 answer
657 views

tRAS definition for DDR memory

1 vote
1 answer
461 views

Why for setup check AND gates use rising edge, while OR gates use falling edge and vice versa for hold check in clock gating?

1 vote
0 answers
110 views

opamp simulation

1 vote
0 answers
853 views

Unitary property of scattering matrix

0 votes
0 answers
801 views

Proof of Bode-Fano criterion

0 votes
1 answer
865 views

Verilog negation operator on inout-type signals

0 votes
2 answers
452 views

IMPACT : Can't open /dev/parport0: No such file or directory

0 votes
1 answer
102 views

Chipscope ILA unable to capture signals correctly

0 votes
0 answers
105 views

Xilinx primitives for DDR3 memory controller

0 votes
0 answers
58 views

Xilinx ISE implementation stage issues

0 votes
1 answer
90 views

Question about shortest-path algorithm during synchronous circuit synthesis

0 votes
1 answer
167 views

SDC constraint inside Xilinx ISE

0 votes
1 answer
153 views

Stability Criteria of Type 3 Digital PLL

-2 votes
1 answer
314 views

Additive latency for DRAM READ and WRITE commands [closed]