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dave_59
  • Member for 10 years, 1 month
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9 votes
Accepted

Nonblocking ++ equivalent in SystemVerilog

8 votes
Accepted

Verilog - Use integer constant to define signal width

8 votes

Lint tool is throwing an error about bit width when adding two 10-bit unsigned numbers and assigning to a 11-bit net

7 votes
Accepted

How to declare a global variable in Verilog

7 votes
Accepted

Is it necessary to declare reg before assignment in Verilog?

7 votes

Is (BC + AD)<<16 equivalent to (BC << 16) + (AD <<16)?

7 votes
Accepted

Is it possible to use conditional statements to modify parameters at compile time in Verilog?

7 votes

Are there any free simulators for SystemVerilog?

6 votes

"Register is illegal in left-hand side of continuous assignment" in modelsim but not verilator

6 votes

Multiplying signed to unsigned binary numbers in verilog

6 votes
Accepted

Verilog - Can you `define a bit slice?

6 votes
Accepted

Is it a good practice to define TRUE/FALSE constants in SystemVerilog?

6 votes
Accepted

Basic addition not working as expected

6 votes
Accepted

What does it mean when there's a minus sign in front of a signal?

6 votes
Accepted

What's the point of memory compilers like OpenRAM or Synopsys Memory Compiler?

5 votes

How can I get rid of warnings in Verilog code for 32-bus 8:1 mux?

5 votes

SystemVerilog array initialization

5 votes

What can procedural statements do that assignment statements cannot do in Verilog?

5 votes
Accepted

Why does adding "& 1" to an assign statement produce a completely different synthesis?

5 votes
Accepted

Strange thing with concatenation and adding in Verilog

5 votes
Accepted

Are rippling designs synthesizable in Verilog?

5 votes

Verilog for loop - genvar vs int

5 votes
Accepted

Error: HDL-Complier-661 Non-net port cannot be mode of input

5 votes
Accepted

Net type, variable type, data type and data objects

5 votes

How to write 'a signal should never have certain value before it attains some other value' in SystemVerilog assertion?

5 votes
Accepted

Relation between RTL and Verilog modules

4 votes
Accepted

SystemVerilog: How to give different parameters to modules in the same array?

4 votes

Verilog - Name is optional when instantiating primitive gates

4 votes

$random in Verilog doesn't seem to be working

4 votes
Accepted

Active low vs active High reset in CPLD

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