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Anarkie
  • Member for 8 years, 2 months
  • Last seen more than 3 years ago
9 votes
3 answers
2k views

Pressing same key rows at the same time

2 votes
2 answers
7k views

Generate State Diagram from VHDL Code?

2 votes
3 answers
1k views

Set a constant high signal to low

1 vote
3 answers
1k views

Return from idle state

1 vote
1 answer
244 views

Xilinx Design Summary

1 vote
1 answer
1k views

Fixing 1 failing timing constraint in Xilinx

1 vote
1 answer
1k views

Analyzing Xilinx Design Summary?

1 vote
2 answers
11k views

Signal assignment in/out process

1 vote
1 answer
2k views

Key press/Key release

0 votes
1 answer
5k views

Removing warning FF/Latch trimming

0 votes
2 answers
4k views

Usage of UCF file and Clock Divider?

0 votes
1 answer
858 views

Enable clock for a state machine?

0 votes
1 answer
509 views

Signal Generation with duration in VHDL?

0 votes
1 answer
2k views

State switches in FSM

-1 votes
2 answers
619 views

Usage of Next state and Clock Divider?