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  • Member for 9 years, 10 months
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4 votes
3 answers
4k views

How to configure HCI UART for 3 Mbps?

2 votes
0 answers
126 views

FDRE with RST tied to 0 to synthesize a value at reset at 1: hardware value not correct, why?

2 votes
1 answer
1k views

CMOS coin battery drained out in 5min even without the BIOS IC

1 vote
1 answer
78 views

How to stop ModelSim at a condition based on signals?

1 vote
1 answer
633 views

AND Gate and posedge CLK ? simple question

1 vote
1 answer
579 views

How to track down all the registers connected to a specific downstream register? (for set_max_delay's --from)

1 vote
2 answers
128 views

How to hash map known values to smaller data width?

1 vote
2 answers
660 views

Differential inputs ADC:

0 votes
1 answer
701 views

Why does the 10G XGMII specification mention a 32b instead of 64b bus for 156.25MHz?

0 votes
1 answer
187 views

DDR4 DIMM/component, different CL?

0 votes
2 answers
554 views

FT232H: Clock stretching using MPSSE

-1 votes
1 answer
182 views

Which PRBS to use?

-1 votes
1 answer
438 views

Is it possible to use `.*` in SystemVerilog to register interfaces' elements?

-1 votes
1 answer
1k views

External battery for laptop with 18650

-1 votes
2 answers
299 views

Boost /step up converter efficient and very small for high current ? (with example)

-2 votes
2 answers
146 views

How can I run Verilog code with data at a specific time in the past?