user avatar
user avatar
user avatar
Paebbels
  • Member for 8 years
  • Last seen more than a month ago
14 votes
Accepted

Do open source libraries exist for VHDL the way they do for C++ or python?

13 votes

Why implement microcontroller in FPGA?

12 votes

Are there any standard FPGA internal buses?

9 votes

VHDL: is there a way to create an entity into which constants can be passed?

7 votes
Accepted

CDC Synchonisation primitives for an Altera FPGA

6 votes
Accepted

How to read hexadecimal data from text file and write in into memory in verilog?

6 votes
Accepted

Poor clock output from Spartan6 FPGA

6 votes

custom FPGA PCB Design tips

6 votes

Is this BRAM being fully utilized if I use a different data width?

5 votes
Accepted

VHDL "compile time" math?

5 votes

Dividing numbers on an FPGA

5 votes

VHDL: I can port map std_logic_vector to a signed or unsigned port, why?

5 votes
Accepted

VHDL: Declaring an empty array (in a test bench)

5 votes
Accepted

How to interface 1 MSPS ADC with processing module in FPGA?

5 votes

Does a package exist to carry out intense string manipulation in VHDL?

5 votes
Accepted

How to understand the timing report after synthesis?

4 votes

Standard integer width function in VHDL

4 votes

How to solve routing issues in Artix7?

4 votes

How to get the longest one's sequence in verilog

4 votes
Accepted

Clock Domain Crossing for Pulse and Level Signal

4 votes

How do you cast an integer as a time in VHDL?

4 votes
Accepted

ModelSim: Why can't I see generics in simulation?

4 votes

Is there an FPGA chip that has a built-in image sensor (or vice versa)?

3 votes
Accepted

non static error in Precision RTL

3 votes

What exactly is or how does a weak signal come into play in VHDL?

3 votes

How is ASIC design different from FPGA design? Do you write HDL (Verilog, VHDL) to design and ASIC the same way you would for an FPGA?

3 votes
Accepted

How to check output after FPGA Implementation?

3 votes
Accepted

Signed Addition of two std logic vectors while looking for overflow and carry

3 votes
Accepted

Configuring a 7-Series GTXE2 transceiver for Serial-ATA (Gen1/2/3)

3 votes

How does someone initially design a digital system for HDL?