Electrical Engineering
Unreasonable Sin's user avatar
Unreasonable Sin's user avatar
Unreasonable Sin's user avatar
Unreasonable Sin
  • Member for 11 years, 8 months
  • Last seen more than 3 years ago
  • Oregon
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I like numbers.

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3
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3
Posts
60
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1
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20
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All Questions Answers
Score Newest
answer
3
Continuous assignment during SystemVerilog simulation
Sep 23, 2013
question
2
Continuous assignment during SystemVerilog simulation
Sep 23, 2013
question
2
Instantiating Parameterized Modules in SystemVerilog
Jul 18, 2014
question
1
NTE912 Pinout Confusion
Dec 10, 2013
question
0
ioProx ID card continually getting fried
May 4, 2012
Top network posts
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8
Favourite open problem?
7
Combinations and Permutations Question
6
Simplify fraction - Where did the rest go?
6
Who is the Youngster in the Automorphic Room?
6
What are some good introductory textbooks on Sieve Theory?

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