User TEMLIB

23 votes

VHDL: Why is it hard to design a floating point unit in hardware?

answered May 19, 2019 at 20:33

12 votes

Accepted

VHDL: What is correct way to model open collector output for FPGA?

answered Jun 13, 2019 at 20:40

10 votes

Accepted

Why do the television manufacturers (Samsung, Sony, LG, so on) exceed the voltage capacity on LED strips (backlight) on TVs?

answered May 26, 2020 at 22:44

10 votes

What is DMIPS/MHz?

answered Aug 18, 2020 at 8:55

10 votes

Is there any way to use half-bits?

answered Nov 22, 2014 at 21:12

10 votes

Accepted

Why do I need a page directory?

answered Sep 29, 2015 at 18:31

9 votes

Why should we use 3.3 V instead of 3 V?

answered Jan 24, 2021 at 13:54

7 votes

Why are the SRAM data and address pins numbered?

answered Sep 22, 2018 at 8:55

7 votes

Accepted

Verilog - Synthesize High Speed Leading Zero Count

answered Oct 24, 2015 at 0:31

7 votes

VHDL how to make a redundant case statement simpler?

answered Aug 28, 2015 at 22:10

7 votes

Why is Ethernet So Power Hungry?

answered Jan 10, 2015 at 14:14

6 votes

Sine wave to square wave - Schmitt trigger

answered Apr 5, 2015 at 14:22

6 votes

Why does hardware division take much longer than multiplication?

answered Jan 16, 2017 at 21:30

5 votes

Single issue and Dual issue architecture

answered Dec 26, 2014 at 11:17

5 votes

Accepted

How many transistors are there in a logic gate?

answered Jun 29, 2019 at 16:09

4 votes

Accepted

Is dram constantly refreshing during windows sleeps?

answered Apr 21, 2020 at 20:28

4 votes

What tasks does Graphics hardware perform and what steps does it follow to do so

answered Jan 7, 2015 at 1:48

4 votes

Purpose of the magnetics center tap in Ethernet

answered Mar 10, 2015 at 20:45

4 votes

How voltage is related to frequency in CPU?

answered Dec 3, 2017 at 18:15

4 votes

Why didn't 1000BASE-TX gain more popularity than 1000BASE-T?

answered Dec 1, 2015 at 21:43

3 votes

VHDL - using PORT MAP in CASE?

answered Dec 7, 2015 at 1:46

3 votes

Difference between Micro-Operations in RISC and CISC processors

answered Aug 31, 2015 at 20:27

3 votes

Accepted

VHDL generate statement increment by 2

answered Sep 7, 2015 at 20:36

3 votes

How to decrease used LUTs in FPGA Design?

answered Jul 30, 2017 at 10:31

3 votes

Why Xilinx ISE doesn't infer Block Ram for this Array?

answered Aug 6, 2017 at 10:45

3 votes

Accepted

How does CPU read data from the RAM?

answered Mar 14, 2015 at 0:11

3 votes

FCS verification of ethernet frame

answered May 15, 2015 at 21:32

3 votes

How to find the expression for Vout?

answered Oct 23, 2014 at 0:02

3 votes

Accepted

5-stage pipelined implementation (RISC) of a microprocessor

answered Oct 15, 2014 at 22:09

3 votes

Accepted

Neutron Single Event Upset (NSEU) how its effect is mitigated in electronics in space vehicles?

answered Dec 23, 2016 at 11:57

Stack Exchange Network

110 Answers

VHDL: Why is it hard to design a floating point unit in hardware?

VHDL: What is correct way to model open collector output for FPGA?

Why do the television manufacturers (Samsung, Sony, LG, so on) exceed the voltage capacity on LED strips (backlight) on TVs?

What is DMIPS/MHz?

Is there any way to use half-bits?

Why do I need a page directory?

Why should we use 3.3 V instead of 3 V?

Why are the SRAM data and address pins numbered?

Verilog - Synthesize High Speed Leading Zero Count

VHDL how to make a redundant case statement simpler?

Why is Ethernet So Power Hungry?

Sine wave to square wave - Schmitt trigger

Why does hardware division take much longer than multiplication?

Single issue and Dual issue architecture

How many transistors are there in a logic gate?

Is dram constantly refreshing during windows sleeps?

What tasks does Graphics hardware perform and what steps does it follow to do so

Purpose of the magnetics center tap in Ethernet

How voltage is related to frequency in CPU?

Why didn't 1000BASE-TX gain more popularity than 1000BASE-T?

VHDL - using PORT MAP in CASE?

Difference between Micro-Operations in RISC and CISC processors

VHDL generate statement increment by 2

How to decrease used LUTs in FPGA Design?

Why Xilinx ISE doesn't infer Block Ram for this Array?

How does CPU read data from the RAM?

FCS verification of ethernet frame

How to find the expression for Vout?

5-stage pipelined implementation (RISC) of a microprocessor

Neutron Single Event Upset (NSEU) how its effect is mitigated in electronics in space vehicles?