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user2913869
  • Member for 7 years, 10 months
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3 votes

Can poor hobbyists utilise FPGAs?

3 votes
Accepted

Problem in understanding bridge rectifier

3 votes

VHDL Algorithm state machine output

2 votes

FPGA: possible to use PC as I/O?

2 votes
Accepted

Arduino and SSR to drive 12V solenoid

2 votes

Eliminate VHDL inferred latch in case statement

1 vote

Writing synthesizable testbenches

1 vote

SDRAM timing confusion

1 vote

In digital logic, when given a requirement of a 64 byte FIFO, is it possible to calculate the width and depth?

1 vote

Will the High-Level Synthesis (HLS) design approach for FPGAs reduce the demand for RTL designers?

1 vote

Build a "gate" that passes only one risinge edge

1 vote

How to cross clock domains efficiently?

1 vote

Confusion about connection/symbol to air-flow switch

1 vote

Switch ON with PushButton, Switch off with GPIO

0 votes

Need help understanding this circuit (with LUTs, multiplexer and flip-flops)

0 votes

Add with carry in VHDL + operator

0 votes

Discrepancy between RTL schematic and Behavioral simulation in Vivado