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Electrical Engineering
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John
  • Member for 12 years, 11 months
  • Last seen more than 6 years ago
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9
Reverse engineering the manufacturer's programming sequence of an FPGA
Feb 28, 2017
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4
Is there an example of a Mealy state machine that can not be converted to a Moore?
Nov 11, 2016
answer
3
Does nodal analysis work with alternating currents if every step is treated like DC?
Mar 18, 2013
answer
3
Why delays cannot be synthesized in Verilog?
Jul 14, 2014
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2
Simplify a logic expression - Where have I gone wrong?
Aug 18, 2014
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2
Transfer function of a rotary encoder
May 10, 2017
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2
Is it possible to implement RC-5 not using interrupts?
Jun 14, 2017
answer
2
How to interface an ADC with FPGA through the CLKOUT signal in verilog?
Aug 4, 2017
answer
1
State diagram Implementation
Oct 28, 2011
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1
Bandwidth of CW modulation (morse code)?
Jul 22, 2014
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32
Why do faculty use the software "Blackboard"?
19
Countries where lecture duration does not exceed one hour
16
When do we actually use a Trie?
13
Is it frowned upon to have a figure in the introduction of a Masters thesis?
8
Reasons for an academic to need administrator rights on work computer