Electrical Engineering
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John

Apparently, this user prefers to keep an air of mystery about them.

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  • Member for 9 years, 5 months
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  • Last seen Mar 28 '18 at 8:44

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9 Reverse engineering the manufacturer's programming sequence of an FPGA Feb 28 '17
4 Is there an example of a Mealy state machine that can not be converted to a Moore? Nov 11 '16
3 Does nodal analysis work with alternating currents if every step is treated like DC? Mar 18 '13
3 Why delays cannot be synthesized in Verilog? Jul 14 '14
2 Simplify a logic expression - Where have I gone wrong? Aug 18 '14
2 Transfer function of a rotary encoder May 10 '17
2 Is it possible to implement RC-5 not using interrupts? Jun 14 '17
2 How to interface an ADC with FPGA through the CLKOUT signal in verilog? Aug 4 '17
1 How would multiple ADC channels be processed? Jun 14 '17
1 How to create a counter to display 6 digits using anodes? May 16 '17
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