User João Pereira

4 votes

1 answer

5k views

Axi DMA correct parameters

asked Jun 30, 2015 at 15:51

3 votes

1 answer

5k views

Convert C to FPGA

asked Feb 19, 2015 at 17:38

2 votes

1 answer

494 views

Zedboard 512x512 matrices, % utilization problem

asked Jun 3, 2015 at 15:10

2 votes

2 answers

1k views

FPGA Floating-point to Unsigned 32bits

asked Jun 12, 2015 at 14:30

2 votes

1 answer

549 views

Vivado HLS: Is it Xilinx specific?

asked Nov 12, 2015 at 14:43

2 votes

0 answers

2k views

Include libraries in GHDL

asked Nov 24, 2015 at 16:17

2 votes

2 answers

1k views

Figuring out mininum/maximum clock frequency [VHDL]

asked Dec 1, 2015 at 11:39

2 votes

4 answers

6k views

When to use State Machines - FPGA

asked Dec 3, 2015 at 16:15

1 vote

1 answer

978 views

Synthesis tool free-source [closed]

asked Nov 4, 2015 at 13:33

1 vote

1 answer

191 views

Some pointers on how to begin VHDL writing

asked Nov 10, 2015 at 16:31

1 vote

1 answer

4k views

MM2S simple transfer gone wrong

asked May 13, 2015 at 13:14

0 votes

1 answer

474 views

Zedboard clock cycles analysis

asked Jun 5, 2015 at 17:45

0 votes

1 answer

373 views

Pipeline loop with sum

asked Mar 26, 2015 at 16:30

0 votes

1 answer

1k views

Best way to pass floating-point numbers to DDR - Zedboard

asked Apr 13, 2015 at 15:48

0 votes

1 answer

726 views

Memory address 32-bit

asked Apr 20, 2015 at 11:19

0 votes

1 answer

574 views

Understanding Address Map

asked Apr 20, 2015 at 15:38

0 votes

1 answer

2k views

Xilinx ap_axiu parameters

asked Jun 12, 2015 at 17:14

0 votes

1 answer

344 views

Change PL clock

asked Jun 26, 2015 at 11:30

0 votes

2 answers

351 views

Inferring D-latch on Zedboard within Vivado Error

asked Dec 3, 2015 at 12:17

-1 votes

1 answer

76 views

MityDSP and Ephiphany doubts [closed]

asked Feb 19, 2015 at 17:07

Stack Exchange Network

20 Questions

Axi DMA correct parameters

Convert C to FPGA

Zedboard 512x512 matrices, % utilization problem

FPGA Floating-point to Unsigned 32bits

Vivado HLS: Is it Xilinx specific?

Include libraries in GHDL

Figuring out mininum/maximum clock frequency [VHDL]

When to use State Machines - FPGA

Synthesis tool free-source [closed]

Some pointers on how to begin VHDL writing

MM2S simple transfer gone wrong

Zedboard clock cycles analysis

Pipeline loop with sum

Best way to pass floating-point numbers to DDR - Zedboard

Memory address 32-bit

Understanding Address Map

Xilinx ap_axiu parameters

Change PL clock

Inferring D-latch on Zedboard within Vivado Error

MityDSP and Ephiphany doubts [closed]