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Electrical Engineering
Tomas D.'s user avatar
Tomas D.'s user avatar
Tomas D.'s user avatar
Tomas D.
  • Member for 13 years
  • Last seen more than a week ago
  • Michigan
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answer
6
Why are vias placed this way on a PCB?
Jul 30, 2012
answer
6
What is the I/O standard for the PCIe data lines?
Sep 19, 2012
answer
5
Is there any restriction in the choice of Ethernet PHY, depending on the TCP/IP stack?
Oct 4, 2012
answer
4
Merge a differential pair into one signal
Sep 2, 2012
answer
4
How fast does a 64-bit multiply or divide execute on an FPGA?
Dec 21, 2012
answer
4
How to generate wait until division is over in verilog?
Dec 21, 2012
answer
3
what is a transceiver reconfiguration controller on FPGA
May 20, 2013
answer
3
My design is not meeting timing. What can I do?
Oct 12, 2012
answer
2
Multiple DDR3 memory VTT source
Sep 11, 2013
answer
2
Custom SOPC Builder Components in Quartus II
Apr 23, 2013