I work for SynthWorks, a VHDL training company. If you are looking to improve your VHDL verification process, check out our VHDL Testbenches and Verification class at: http://www.synthworks.com/vhdl_testbench_verification.htm
I am also the co-founder and chief architect of the Open Source VHDL Verification Methodology (OSVVM). OSVVM provides constrained random (good), intelligent randomization (better), and functional coverage (essential with any randomization methodology) for VHDL. It is open source and it is free. In our classes, we teach a superset of OSVVM. To learn more, see http://osvvm.org/ and http://www.synthworks.com/blog/osvvm/
I am also the IEEE VHDL working group chair. If you are interested in IEEE VHDL standards, see http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/WebHome. We do our work on the TWIKI site, via email, and phone meetings. Drop me an email (see below) and I will get you set up. If you are answering VHDL questions here, don't be surprised if I contact you - it is the way I recruit volunteers.
email: jim at synthworks dot com