Good point, I added a comment in the initial post to specify input and load. What do you mean that they could rely on some disconnection when the incoming power isn't present? Btw, the wire going toward the top, and the one toward the bottom, they go to not populated footprints.

Thank you for looking at it. The MOSFETs in the pictures you sent have their source toward the load (it is the other way around in the NVIDIA design). And the control circuit is also different in NVIDIA design. I'm not sure how they relate then?

Thank you Rick for your answer and the few keys about the involved underlying concepts! Some extra research brought me to this article which helped me visualize the behavior (even if it is a different simulation). To make a connection between the Photon's answer and yours, how does the distance between L3 and L4 matter for option B and C? Even though I believe that a binary answer may be too simplistic: below 5 Gbits, would you still consider option B and C as relevant if L3 is about equidistant to L2 and L4?

Thank you. I'm a bit surprised because, if I understood correctly, Rick Hartley actually said in the video I pointed to in my first post that option B would be acceptable up to 2-3 GHz. Are there specific conditions to make it work as he suggested? I understand the general statement that a gap in a reference plane is a problem. However, in this case, it seems to me that it exists a very good continuous return path on L2. Why would current try to force its way into L4 then?