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danmcb
  • Member for 7 years, 3 months
  • Last seen this week
  • Antwerp, Belgium
5 votes
3 answers
877 views

Simulation versus Prototyping

4 votes
3 answers
1k views

Using both clock edges in an FPGA design

3 votes
2 answers
1k views

SPI interface on Xilinx FPGA, clock domains and timing constraints

2 votes
1 answer
180 views

old 80C31 circuit not working. EPROM data retention issue?

2 votes
1 answer
131 views

Is there a standard way to put compiled code onto a processor embedded in an FPGA?

1 vote
4 answers
794 views

how long should an I2C slave wait for a STOP bit (if at all)?

1 vote
2 answers
464 views

transient protection for 0.5W laser diode switching driver

1 vote
4 answers
217 views

royalty free embedded processor [closed]

1 vote
1 answer
728 views

How do Vivado and Vitis determine where stack and heap are located?

1 vote
0 answers
1k views

getting STM32F4 working as USB audio/video device

0 votes
1 answer
2k views

Trying to program an STM32 device with ST-LINK_CLI.exe

0 votes
3 answers
191 views

Low risk entry into CPLD/FPGA design? [closed]