Electrical Engineering
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scary_jeff
  • Member for 8 years
  • Last seen this week
  • U.K.
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About

Electronic Engineer spending most of my work time on FPGA designs.

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Top posts
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All Questions Answers
Score Newest
answer
8
Handling inferred clocks during RTL Synthesis
Dec 11, 2017
answer
7
How to resolve VHDL packages constant name clash?
Aug 2, 2019
answer
7
Partially associated formal cannot have actual OPEN in VHDL under Vivado
Jan 22, 2018
answer
7
How does a structural architecture know which entity to use?
Jan 25, 2016
answer
7
Why isn't this decoder being inferred as a LUT?
Aug 26, 2016
answer
6
Pulse on edge of different clock
Dec 8, 2015
answer
6
VHDL Unconstrained port in a entity
Feb 22, 2016
answer
6
Is there a "standard" way to verify HDL of a state machine?
Dec 12, 2016
answer
5
VHDL: port map in process error
Aug 3, 2015
answer
5
Combining components and timing in VHDL (And probably verilog) / FPGA
Sep 4, 2015
Top network posts
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14
How to write an integer to stdout as hexadecimal in VHDL?
11
Variable number of inputs and outputs in VHDL
7
Tips and tricks for vhdl design debugging
7
Object is used but not declared?
7
Get attribute of a field from a VHDL record type

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