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scary_jeff
  • Member for 7 years, 4 months
  • Last seen this week
  • U.K.
8 votes
Accepted

Handling inferred clocks during RTL Synthesis

7 votes

How to resolve VHDL packages constant name clash?

7 votes
Accepted

Partially associated formal cannot have actual OPEN in VHDL under Vivado

7 votes
Accepted

How does a structural architecture know which entity to use?

7 votes
Accepted

Why isn't this decoder being inferred as a LUT?

6 votes
Accepted

Pulse on edge of different clock

6 votes
Accepted

VHDL Unconstrained port in a entity

5 votes

Divide by integer in VHDL

5 votes
Accepted

VHDL: port map in process error

5 votes

Combining components and timing in VHDL (And probably verilog) / FPGA

4 votes
Accepted

Is there a "standard" way to verify HDL of a state machine?

4 votes

Why I do not need to ensure I have no latches in sequential process [VHDL]

4 votes

How to write infinite loop in vhdl?

4 votes
Accepted

VHDL: Demultiplexing a signal to one of many outputs while driving unused outputs to '0'

4 votes

Using VHDL code to design a JK Flip Flop

3 votes
Accepted

With IP-Cores without handshake protocol, how can I verify (VHDL assert?) their latency?

3 votes

Syntax and/or best practice for buffering a vector in Verilog or VHDL

3 votes

Xilinx XST won't infer block ram

3 votes
Accepted

VHDL loop not updating output

3 votes
Accepted

Why can't I connect a std_logic_vector signal to a port of type signed or unsigned

3 votes
Accepted

What is the effect of this delayed statement in the following process?

3 votes
Accepted

Clock Generation in modelsim

3 votes
Accepted

TEXTIO : Read past end of file in ModelSim Simulation

3 votes

VHDL signal assignement

3 votes
Accepted

VHDL: value isn't assigned immediately

2 votes

Crossing a single-cycle spike signal from a fast clock domain to a slower one

2 votes

Constant value required for VHDL array indexing?

2 votes

VHDL port map: connect only some bits of a vector

2 votes

Clock port and any other port of a register should not be driven by the same signal source

2 votes

How to get the most significant bit being one in VHDL?