User user8469759

5 votes

1 answer

3k views

VHDL functions with generic or "run time variable", synthesis issues

asked Sep 10, 2015 at 12:00

5 votes

0 answers

566 views

Floating point addition. Are guard, round and sticky bit always necessaryl? analysis of a special case

asked Sep 8, 2016 at 8:46

3 votes

2 answers

6k views

Identifier not declared in generic map, vhdl

asked Nov 3, 2015 at 12:47

3 votes

1 answer

11k views

Serial Adder vhdl design

asked Sep 21, 2015 at 10:54

3 votes

3 answers

11k views

Numeric literal constant in VHDL treatment

asked Nov 19, 2015 at 9:27

3 votes

3 answers

8k views

VHDL if generate in the preamble, is it possible?

asked Jun 2, 2016 at 9:19

2 votes

1 answer

1k views

illegal reference of a signal during a static elaboration, vhdl

asked Oct 30, 2015 at 16:08

2 votes

1 answer

5k views

Understanding type conversion in expression in vhdl

asked Nov 2, 2015 at 9:41

2 votes

2 answers

2k views

VHDL difference between component and subprogram

asked Apr 14, 2015 at 10:53

2 votes

1 answer

368 views

Multioperand pipelined adder

asked Sep 17, 2015 at 12:01

2 votes

0 answers

275 views

Operator synthesis VHDL, numeric_std.vhd

asked Sep 17, 2015 at 13:36

2 votes

1 answer

423 views

Recursion in VHDL, performance? what is the difference with a conventional programming language?

asked Sep 21, 2015 at 9:53

2 votes

1 answer

212 views

What is the effect of this delayed statement in the following process?

asked Sep 7, 2015 at 10:56

2 votes

2 answers

3k views

SRT division vs Non restoring division

asked Sep 4, 2016 at 14:30

2 votes

0 answers

249 views

Ling adder vs classic CLA adder what's the difference?

asked Mar 30, 2017 at 12:30

1 vote

1 answer

273 views

Understanding data-flows graph

asked Sep 26, 2016 at 13:24

1 vote

2 answers

497 views

Low cost FPGA and EDA tools? costs?

asked Oct 29, 2016 at 13:38

1 vote

1 answer

985 views

Mixing structural and behavioral in VHDL, does it make sense?

asked Nov 3, 2016 at 13:38

1 vote

1 answer

456 views

Silly serial adder design with control unit

asked Mar 23, 2017 at 17:05

1 vote

1 answer

314 views

VHDL simulation full adder, timing question

asked Aug 2, 2016 at 9:33

1 vote

2 answers

5k views

VHDL serial adder test bench return UUUU

asked Sep 30, 2015 at 9:33

1 vote

2 answers

2k views

Constant value required for VHDL array indexing?

asked Oct 9, 2015 at 9:04

1 vote

1 answer

5k views

loop synthesis vhdl

asked Oct 12, 2015 at 13:53

1 vote

2 answers

2k views

Difference between cordic algorithm and table based methods for elementary functions computation

asked Jul 6, 2016 at 12:55

0 votes

1 answer

287 views

How can I simulate this vhdl using modelsim?

asked Jul 28, 2016 at 9:07

0 votes

2 answers

60 views

Verilog, Is this statement interpreted as I expect?

asked Jul 29, 2016 at 12:53

0 votes

1 answer

2k views

Test bench with IO file vhdl

asked Jul 28, 2015 at 14:07

0 votes

1 answer

172 views

Bad design of shift register

asked Sep 21, 2015 at 13:11

0 votes

1 answer

115 views

On-line arithmetic vs digit recurrence, are they different?

asked Aug 24, 2016 at 13:52

0 votes

1 answer

188 views

Ripple carry adder, analysis of error propagation

asked Aug 26, 2016 at 10:45

Stack Exchange Network

36 Questions

VHDL functions with generic or "run time variable", synthesis issues

Floating point addition. Are guard, round and sticky bit always necessaryl? analysis of a special case

Identifier not declared in generic map, vhdl

Serial Adder vhdl design

Numeric literal constant in VHDL treatment

VHDL if generate in the preamble, is it possible?

illegal reference of a signal during a static elaboration, vhdl

Understanding type conversion in expression in vhdl

VHDL difference between component and subprogram

Multioperand pipelined adder

Operator synthesis VHDL, numeric_std.vhd

Recursion in VHDL, performance? what is the difference with a conventional programming language?

What is the effect of this delayed statement in the following process?

SRT division vs Non restoring division

Ling adder vs classic CLA adder what's the difference?

Understanding data-flows graph

Low cost FPGA and EDA tools? costs?

Mixing structural and behavioral in VHDL, does it make sense?

Silly serial adder design with control unit

VHDL simulation full adder, timing question

VHDL serial adder test bench return UUUU

Constant value required for VHDL array indexing?

loop synthesis vhdl

Difference between cordic algorithm and table based methods for elementary functions computation

How can I simulate this vhdl using modelsim?

Verilog, Is this statement interpreted as I expect?

Test bench with IO file vhdl

Bad design of shift register

On-line arithmetic vs digit recurrence, are they different?

Ripple carry adder, analysis of error propagation