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toolic
  • Member for 7 years, 2 months
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13 votes
Accepted

In FPGAs, is it safe to execute non-blocking assignments like `b <= a; a <= 0;` in the same clock cycle?

6 votes
Accepted

Why don't I see the clocking block input skew in waveforms?

4 votes

Why is my code output always showing 0?

4 votes

Defining a variable in bytes using Verilog

4 votes
Accepted

Is it necessary to take into account the actual state of a combinational circuit's signals to calculate its maximum delay?

4 votes
Accepted

ISE Design Suite simulation problem

4 votes
Accepted

Result is XXXXXXXXXXXX for Verilog

3 votes

0110 moore overlapping in verilog

3 votes
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Quirk of simulation or quirk of Verilog?

3 votes
Accepted

Verilog if-else-if syntax

3 votes
Accepted

Parametric bit-width assignment in Verilog

3 votes
Accepted

What is the new constructor's argument rule in UVM?

3 votes

'1011' Overlapping (Moore) Sequence Detector in Verilog

3 votes
Accepted

Verilog procedural assignment reg guaranteed to keep value when not assigned?

3 votes

Verilog counter does not work

3 votes
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Verilog output is hiZ in testbench

2 votes
Accepted

Verilog code "always @" block not working as expected

2 votes
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Finite State Machine

2 votes

How does strength work in Verilog?

2 votes
Accepted

Systemverilog size attributes

2 votes
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Error while implemeting D_FF from JK_FF in Verilog

2 votes
Accepted

How to generate 1 second clock using verilog for Artix 7 with frequency of 100 MHz

2 votes

What happens when the number of bits required to represent possible values in constraint (var inside {[x:y]};) exceed the rand variable width?

2 votes
Accepted

Coarse counter giving incorrect pulse length measurements at high frequencies

2 votes
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How to use case for continuous assignment?

2 votes
Accepted

Ternary operator doesn't work in Icarus Verilog

2 votes
Accepted

SystemVerilog - clk not toggling in verification

2 votes
Accepted

How to connect multiple interfaces within DUT in UVM?

2 votes
Accepted

Does declaring Verilog arrays with indices in different directions makes any difference?

2 votes
Accepted

How to partial port connect by using interface bundle?